#!/usr/bin/perl

use    warnings;
#####*****     Defining Required Classes     *****####################
+##########



package signal;
    sub _define{
        my    $type    =    shift    ;
        my    $name    =    shift    ;    
        my    $width    =    shift    ;

        if(($type ne "reg") && ($type ne "wire"))    {
            printf("\n***** ERROR: Wrong Signal type %s\n",$type);
            exit(1);
        }

        my    $object =    {    type    =>    $type    ,
                            name    =>    $name    ,
                            width    =>    $width    };
                    
        bless($object,signal);
        return $object;
    }

package signal;
    sub print_defn    {
        my $self    =    shift;
        printf("\t%s",$self->{type});
        if(($self->{width})!=1)    {
            printf("\t[%d:0]",($self->{width})-1)
        }
        else {
            print("     ");
        }
        printf("\t\t\t%s;\n",$self->{name});
    }

package    port;
    sub _define{
        my $direction    =    shift    ;
        my $name    =    shift    ;
        my $width    =    shift    ;

        my $object =    {    direction    =>    $direction    ,
                            name        =>    $name        ,
                            width        =>    $width        };
                    
        bless($object,port);
        return $object;        
    }

package    port;
    sub print_defn    {
        my $self    =    shift;
        printf("\t%s",$self->{direction});
        if(($self->{width})!=1)    {
            printf("\t[%d:0]",($self->{width})-1)
        }
        else {
            print("     ");
        }
        printf("\t\t\t%s\t\t;\n",$self->{name});
    }

package    connection;
    sub _define{
        my $port    =    shift    ;
        my $signal    =    shift    ;

        my $object    =    {    port            =>    $port    ,
                            signal            =>    $signal    };

        bless($object,connection);
        return $object;        
        
    }

package module;
    sub _define{
        my $name    = shift;
        my $object =    {    name            =>    $name    ,
                            port_list        =>    ()        ,
                            verilog_list    =>    ()        ,
                            signal_list        =>    ()        ,
                            instance_list    =>    ()        };
        print $object->{port_list};
        bless($object,module);
        return $object;        
    }

package module;
    sub    add_port{
        my $self        =    shift    ;
        my $direction    =    shift    ;
        my $name        =    shift    ;
        my $width        =    shift    ;
        my $port =    port::_define($direction,$name,$width);
        push(@{$self{port_list}},$port);
    }

package module;
    sub    add_signal{
        my $self        =    shift    ;
        my $type        =    shift    ;
        my $name        =    shift    ;
        my $width        =    shift    ;
        my $signal         =    signal::_define($type,$name,$width);
        push(@{$self{signal_list}},$signal);
    }

package module;
    sub    add_verilog{
        my $self        =    shift    ;
        my $verilog        =    shift    ;
        push(@{$self{verilog_list}},$verilog);
    }

package    module;
    sub print_defn{
        my $self    =    shift;
        printf("%s\t(",$self->{name});
        foreach my $port (@{$self{port_list}})    {
            $port->print_defn();
        } 
        foreach my $signal (@{$self{signal_list}})    {
            $signal->print_defn();
        } 
        foreach my $verilog (@{$self{verilog_list}})    {
            #print "verilog\n ${$verilog}";
            print $verilog; 
        }

         
        my $size=@{$self{port_list}};
        print "No of ports $size\n";
    }


#package instance;
#    sub    _define {
#        my $module    =    shift    ;
#        my $name    =    shift    ;
#
#        my $object =    {    module            =>    $module    ,
#                            name            =>    $name    ,
#                            connection_list    =>    []        };
#
#        #print $module;
#        #print $object->{module}{port_list};
#        $sample    = $object->{module};
#        print $sample;
#        $sample =$sample->{port_list};
#        print $sample;
#        #$arraaya= @{$sample};
#        #print "here".$arraaya;
#        #print $sample[4];
#
#        
#        $jack=$jack{port_list};
#    #    $size    = @{$jack};
#
#    #    print "size $size";
#    #    
#    #    #print @{$jack}[4];
#
#    #
#
#        #foreach $port (@{$object->{module}->{port_list}}){
#        foreach $port (@{$sample}){
#            print "gere";
#            $port->print_defn();
#        }
#        bless($object,instance);
#        return $object;        
#
#    }

#package    instance;
#    sub    create_empty_connections{
#        my $self    =    shift    ;
#        foreach $port ($self->{module->}){
#            
#        }
#    }

######*****     Main Program    *****#################################
+###########


$module    = module::_define('mem','game');
$module->add_port("input","addr",6);
$module->add_port("input","WR",6);
$module->add_port("input","dd",6);
$module->add_port("input","dddr",6);
$module->add_signal("wire","a",6);
$module->add_signal("wire","b",6);
$module->add_signal("wire","b",6);
$module->add_signal("wire","d",6);
$module->add_signal("reg","e",6);
$module->add_signal("reg","e",6);
$module->add_signal("reg","e",6);

$verilog="
case(cx_state)
    1'b0:
        nx=    1'b1;
    1'b1:
        nx=    1'b0;
    default:
        nx=    1'b0;
";
$module->add_verilog($verilog);

$verilog    ="
always @(posedge clk)
if (!resetn)
    cx_state <=0    ;
else
    cx_state <= nx    ;
";
$module->add_verilog($verilog);
$module->print_defn();


print "START\n";
$size        =    @{$module{port_list}};
print "size=".$size."\n";

#use Scalar::Util 'reftype';
#@ref        =    @{$module->{port_list}};
#$reftype    =    reftype ($ref);
#print $reftype."_ref\n";


print "\n\n\n***END***\n\n\n";
[download]

OUTPUT is

 
[afe_co6] lxcf1:/home/gajbhis/memory > ./n_mw.pl
verilog_listmem (       input   [5:0]                   addr          
+  ;
        input   [5:0]                   WR              ;
        input   [5:0]                   dd              ;
        input   [5:0]                   dddr            ;
        wire    [5:0]                   a;
        wire    [5:0]                   b;
        wire    [5:0]                   b;
        wire    [5:0]                   d;
        reg     [5:0]                   e;
        reg     [5:0]                   e;
        reg     [5:0]                   e;

case(cx_state)
        1'b0:
                nx=     1'b1;
        1'b1:
                nx=     1'b0;
        default:
                nx=     1'b0;

always @(posedge clk)
if (!resetn)
        cx_state <=0    ;
else
        cx_state <= nx  ;
No of ports 4
START
Use of uninitialized value in array dereference at ./n_mw.pl line 232.
Use of uninitialized value in concatenation (.) or string at ./n_mw.pl
+ line 233.
size=



***END***
[download]

Can you tell me why is this prblem with method and call made outside

---

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