Dear Monks, I want to use perl to generate a VHDL code, I have a design that has some generic parameters and I want to generate a code that takes these parameters and generate the code for me,is there any chance to do this properly on perl ?! I am totally new to perl, and in fact I do not know how to do this on perl. one hint about the parameters, one parameter has only one value, but the other has several values. I cannot wait to get a reply ! Hitman

In reply to perl to generate VHDL code by Hitman450

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