This is less Solaris and more (Ultra)SPARC architecture, and that paper discusses some "OS" I've never heard of, "NetraDPS". I found some UltraSparc CPU documentation, but it is somewhat vague on the memory accesses issued by a CASX (or CASXA) instruction.

My vague interpretation of D.2.5.3 is that a CASX instruction will fetch the appropriate page into L2 cache if it is not already there, and then perform the exchange only in the L2 cache, and not force an immediate write-back to the main RAM. This somewhat matches the error behaviour from 16.9.1.7, where a conflict between ECC corrections and CASX instructions on writeback may occur.

In reply to Re: OT: Solaris expertise? by Corion
in thread OT: Solaris expertise? by BrowserUk

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