ravimartha:

I think I'd process it into a set of Karnaugh maps (one per output variable). From there, it's relatively straightforward to create expressions. Your biggest problem might be parsing the verilog.

Update: Repaired link.

...roboticus

When your only tool is a hammer, all problems look like your thumb.

In reply to Re: Coverting Case statements of verilog to equations. by roboticus
in thread Coverting Case statements of verilog to equations. by ravimartha

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