Since your code looks almost like Verilog, have you considered using a Verilog parser? Verilog-Perl and vppreproc in particular may help you weed out comments.

Also, the Verilog $printtimescale system task can be used inside Verilog source code to show the timescale for each module.

In reply to Re: Extracting pattern from a file (Verilog) by toolic
in thread Extracting pattern from a file by ghosh123

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