Hello We have a Hardware design (A ALU model) implemented in verilog RTL and for the same design we have a reference model in perl. Now I have a testbench in Systemc/C++ and I would like to use this perl reference model with in the c++ code and access the reference model subroutines to get the necessary info for checking the hardware design. At the same time the perl reference model also try to access few functions and variable of the testbench which are in c/c++. How do I get this bidirectional communication work. If I add a perl interpreter in my systemc model and run the reference perl model in one of the systemc threads, then I can only access reference model subroutines but on the other side the reference model cannot access the functions and variables from systemc side (I am not sure). How do I solve this? I really need some sugestions on this. Appreciate your help Thanks madala