Thanks Graff for your patient instruction and comments.
For the verilog syntax, you can check here: http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html
In the section of "6.0 Module Port Declarations" you will know the port size definition.

my code @digits ne '' might be a mistake, thanks for pointing it out. I supposed to do nothing if @digits contains no vars. You know otherwise, it would be warning msg prompted saying not a number index assign to $reg32set

Regarding to your code, I think you idear is great. But I had to change the code $#reg32set in  for my $seq (0 .. $#reg32set) to 31 get what I need. The max index is always 32. By the way, you coding style is pretty good and I am trying to learn from you.

Thanks again for everyone comments, and tolerating my confusing explanation. :)

Hanken