$ ls i2c
i2c_master_top.v
$ vhier -y i2c --modules i2c_master_top.v
  i2c_master_top
[download]

The vhier command line is a lot like your favorite Verilog simulator command line. +incdir+ is used only when Verilog source code files include other source code files using the `include compiler directive.

Update: I thought this looked familiar: Re^4: verilog perl usage

Hi toolic I am trying to give a particular directory for vhier to search for the include directories and libraries The usage is vhier +incdir+dir. This translates to what I give on the command prompt, I am in a directory just above i2c( vhier +incdir+./i2c --modules i2c_master_top.v).this gives that it cannot find i2c. I have tried a lot of options on the command prompt like vhier --II<./i2c> and vhier +incdir+I<./i2c>. This usage is mentioned in vhier script itself(downloaded from cpan version 3.110) wonder if you could throw some light on how to give the option for the include directories.would really appreciate it. thanks for your time

i am using this particular program to find the which modules are referenced and which are defined

#!/usr/bin/perl
use Verilog::Netlist;
# set up options so that files can be found
use Verilog::Getopt;
#push(@INC,'pwd');
my $opt=new Verilog::Getopt;
$opt->parameter("-y","i2c",);

# prepare netlist
#$file='home/vp/roopa/i2c/i2c_master_byte_ctrl.v';
my $nl=new Verilog::Netlist(options=>$opt);
foreach my $file('/home/vp/roopa/i2c/i2c_master_top.v')
   {
     $nl->read_file(filename=>$file);

   }
#read in any sub modules
     $nl->link();
     $nl->lint();
     $nl->exit_if_error();
foreach my $mod($nl->top_modules_sorted)
                {
                show_hier($mod, " ","","");
                }

sub show_hier
{

my $mod=shift;
my $indent=shift;
my $hier =shift;
my $cellname=shift;
if(!$cellname)
{
$hier=$mod->name;
#print "\n",$hier;
}
else
{
$hier.=".$cellname";
}
printf("%45s %s\n",$indent."Module ".$mod->name,$hier);

    foreach my$cell($mod->cells_sorted)
    {
    printf($indent."    Cell %s\n", $cell->name);
    
show_hier($cell->submod,$indent." ", hier,$cell->name) if $cell->submo
+d;
    }
}
[download]

Apologize if it is difficult to read becoz of the indentation.copy paste in windows from vi!

OUTPUT

Module i2c_master_top i2c_master_top
     Cell byte_controller
                  Module i2c_master_byte_ctrl i2c_master_top.byte_cont
+roller
      Cell bit_controller
                   Module i2c_master_bit_ctrl i2c_master_top.byte_cont
+roller.bit_controller
     Cell myarbiter
                               Module arbiter i2c_master_top.myarbiter
     Cell mypli1
                                 Module mypli i2c_master_top.mypli1
                                 Module mymux mymux
[download]

The script identifies all the modules defined and referenced. The O/p is interpreted as folllows i2c_master_top.v has the following referenced modules-(the ones given as cells)hierarchy given by top_module.cellname

i2c_master_byte_ctrl
i2c_master_bit_ctrl
myarbiter
mypli
[download]

The problem lies with the module mymux The module mymux is defined in i2c_master_byte_ctrl.v But it shows up as a module in i2c_master_top whereas it is defined only in the child module Only if I remove the mymux module from i2c_master_byte_ctrl,then it does not show I first thought that just comparing the outputs from each file would give me the modules which have been duplicated. But mymux is not duplicated and still it shows up in the outputs of i2c_master_top and i2c_master_byte_ctrl. Could you please help me with this? Thanks for your time

Since I do not have your Verilog files, I can not reproduce your problem.

However, when I add the strictures to your code (use warnings; use strict;), I get a warning message:

Bareword "hier" not allowed while "strict subs" is in use at ...
[download]

Although I doubt this is your problem, try fixing your code like this by adding the single quotes:

show_hier($cell->submod, $indent." ", 'hier', $cell->name) if $cell->s
+ubmod;
[download]

Is there anything special about the "mymux" module? Is it wrapped inside `celldefine compiler directives, for example?

Since I have never used Verilog::Netlist, I can not offer you more specific information about its usage. You might try browsing (or asking a question on) the CPAN Verilog Discussion forum: http://www.cpanforum.com/dist/Verilog-Perl. It's too bad the module author is not a PerlMonk :)