My vague interpretation of D.2.5.3 is that a CASX instruction will fetch the appropriate page into L2 cache if it is not already there, and then perform the exchange only in the L2 cache, and not force an immediate write-back to the main RAM.

Thank you for the link and your interpretation. It still took a while for the penny to drop, but it has now.

On the T1 & T2, L1 (instruction & data) caches are per core. The L2 cache is shared between all cores. Compare & swap instructions are specifically designed for intra-thread & intra-core signalling, they therefore have to be coherent at the L2 cache.

The L2 cache coherency requirement is what causes their high latency; that they only affect a single L2 cache line, their low impact; thus making them perfect for the task of reducing spin-lock 'burn'.

Now to seek out the equivalent X64 instruction :)