in reply to Re^3: Someone please verify this. (Verilog::VCD)
in thread Someone please verify this.

Thanks for your reply. I do have a requirement to create a VCD from a dump of values (a set of samples captured from an on chip memory) -- so that it is better from readability/debug point of view. Hopefully, when i am done with my script, i can contribute some CreateVCD module -- lets see :) Thanks.
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Re^5: Someone please verify this. (Verilog::VCD)
by vijayvithal (Novice) on May 19, 2017 at 17:19 UTC