clk_cts
  |
  |--cts_inst1
         |--CTB02Q
  |--cts_inst2
         |--CTB02Q

##</code><code>##

sub trace_sig_down_hier {

  my $vdb=shift;
  my $module=shift;
  my $signal=shift;
  my $instance=shift;
  my $level=shift;

  print "DEBUG: $module:$module:$signal:$instance:$level\n";
  my($imod,$iname,$port,$l,@connections);


  SIG:foreach my $sig (sort &rvp::get_modules_signals($vdb,$module)) {
	next SIG if ($sig ne $signal);
	
	for (($imod,$iname,$port,$l) = 
	     &rvp::get_first_signal_port_con($vdb,$module,$sig );
	     $imod;
	     ($imod,$iname,$port,$l) = 
	     &rvp::get_next_signal_port_con($vdb)) {
	  print "DC:$imod,$iname,$port,\n";
	  if(&rvp::module_exists($vdb,$module)) {
		my $full_path =  $instance . "/" . $iname;
		$level++;
		my @sub_conns = &trace_sig_down_hier($vdb,$imod,$port,$full_path,$level);
		push @connections,@sub_conns;
	  }
	  my $sig_path;
	  if ($instance) {
		$sig_path = $instance . "/" . $port;
	  }else{
		$sig_path = $module . "/" . $port;
	  }
	  push @connections, $sig_path;
	  #print "SUB : $sig_path\n";
	}
  }

  return @connections;
}

##</code><code>##

11:57_dcollins_HOME_[267]>./tk_verilog.pl
HL: no_gated_clk_cts_1:no_gated_clk_cts_1:
5 : clk_cts
DEBUG: no_gated_clk_cts_1:no_gated_clk_cts_1:clk_cts:no_gated_clk_cts_1:0
DC:cts_env_1,cts_inst,y,
DC:cts_env_1,cts2_inst,y,
DC:cts_env_3,cts3_inst,y,

##</code><code>##

HL: no_gated_clk_cts_1:no_gated_clk_cts_1:
5 : clk_cts
DEBUG: no_gated_clk_cts_1:no_gated_clk_cts_1:clk_cts:no_gated_clk_cts_1:0
DC:cts_env_1,cts_inst,y,
DEBUG: cts_env_1:cts_env_1:y:no_gated_clk_cts_1/cts_inst:1
DC:CTB02Q,cts_inst,Y,
DEBUG: CTB02Q:CTB02Q:Y:no_gated_clk_cts_1/cts_inst/cts_inst:2