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clk_cts | ... |--CTB02Q |--cts_inst2 |--CTB02Q
sub trace_sig_down_hier { ... return @connections; }
11:57_dcollins_HOME_[267]>./tk_verilog.pl HL: no_gated_clk_cts_1:no_gated_clk_cts_1: ... DC:cts_env_1,cts_inst,y, DC:cts_env_1,cts2_inst,y, DC:cts_env_3,cts3_inst,y,
HL: no_gated_clk_cts_1:no_gated_clk_cts_1: 5 : clk_cts ... DEBUG: cts_env_1:cts_env_1:y:no_gated_clk_cts_1/cts_inst:1 DC:CTB02Q,cts_inst,Y, DEBUG: CTB02Q:CTB02Q:Y:no_gated_clk_cts_1/cts_inst/cts_inst:2