in reply to Re^2: extract text from multi-line context (Verilog::VCD)
in thread extract text from multi-line context
use warnings; use strict; use Verilog::VCD qw(:all); my $vcd= parse_vcd('sample.vcd'); for my $code (keys %{ $vcd }) { for my $net (@{ $vcd->{$code}->{nets} }) { print "$net->{name}\n"; for my $aref (@{ $vcd->{$code}{tv} }) { print "@{ $aref }\n"; } } }
It seems like you really only need the signal names, not the times or logic values (except for maybe your BBPLL_CLKO_DIG_96M signal?). Parsing this way gives you all the info you need. You just need to format it the way you want.
It's odd that your VCD file header declares some signals (such as AGC_IF_CAP[2:0]) multiple times. It seems unnecessary.
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Re^4: extract text from multi-line context (Verilog::VCD)
by herman4016 (Acolyte) on Aug 18, 2014 at 02:54 UTC | |
by toolic (Bishop) on Aug 18, 2014 at 13:22 UTC | |
by herman4016 (Acolyte) on Aug 19, 2014 at 02:55 UTC |