in reply to Re^3: extract text from multi-line context (Verilog::VCD)
in thread extract text from multi-line context

That's so Incredible the perl module (Verilog::VCD)! I can get the following data , but how to tranfer to format that I want ? Many thanks !!

VBGOK_H 0 x 3537871350 0 5154695950 x YOUT_RC_CAL 0 x 3537871350 0 5154695950 x CLKO_RXADC_96M 0 x 3537871350 0 5154695950 x AGC_IF_CAP[2:0] 0 xxx 3537871350 111 5154695950 xxx AGC_IF_CAP[2:0] 0 xxx 3537871350 111 5154695950 xxx BBAGC_AVWIN[1:0] 0 xx 3537871350 01 5154695950 xx BBAGC_AVWIN[1:0] 0 xx 3537871350 01 5154695950 xx CKO_HFOSC_2DIV12 0 x 3537871350 0 5154695950 x XO32K_VCOUT 0 x 3537871350 z 5154695950 x YOUT_RC_CAL_PGA 0 x 3537871350 0 5154695950 x ABB_BIAS_EN 0 x 3537871350 1 3537913010 0 3537954670 1 4266046490 0 4448059030 1 5154695950 x TXMIX_EN 0 x 3537871350 0 4448059030 1 5154695950 x BBPLL_CLKO_DIG_96M 0 x 3537871350 0 3537876550 1 3537881760 0 3537886970 1 3537892180 0 3537897390 1 3537902600 0 3537907810 1 3537913020 0 3537918230 1 . . . 5154680220 0 5154685430 1 5154690640 0 5154695850 1 5154695950 x

the format that I want

V0 (BBPLL_CLKO_DIG_96M 0) vsource type=pwl wave=[ 0p 0 199p 0 200p VDD +/2 399p VDD/2 400p 0 599p 0 600p VDD/2 ...... ] V1 (CKO_HFOSC_2DIV12 0) vsource type=pwl wave=[0p 0] V2 (CLKO_RXADC_96M 0) vsource type=pwl wave=[0p 0] V3 (VBGOK_H 0) vsource type=pwl wave=[0p 0] V4 (YOUT_RC_CAL 0) vsource type=pwl wave=[0p 0] V5 (YOUT_RC_CAL_PGA 0) vsource type=pwl wave=[0p 0] V6 (ABB_BIAS_EN 0) vsource type=pwl wave=[0p VDD/2] V7 (TXMIX_EN 0) vsource type=pwl wave=[0p 0] V8 (XO32K_VCOUT 0) vsource type=pwl wave=[0p z] V9 (AGC_IF_CAP\<0\> 0) vsource type=pwl wave=[0p VDD/2] V10 (AGC_IF_CAP\<1\> 0) vsource type=pwl wave=[0p VDD/2] V11(AGC_IF_CAP\<2\> 0) vsource type=pwl wave=[0p VDD/2] V12 (BBAGC_AVWIN\<0\> 0) vsource type=pwl wave=[0p 0] V13 (BBAGC_AVWIN\<1\> 0) vsource type=pwl wave=[0p VDD/2]

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Re^5: extract text from multi-line context (Verilog::VCD)
by toolic (Bishop) on Aug 18, 2014 at 13:22 UTC
    I'm glad you like the module!

    This gets you a little further:

    use warnings; use strict; use Verilog::VCD qw(:all); my $vcd= parse_vcd('sample.vcd'); my $i = 0; for my $code (keys %{ $vcd }) { for my $net (@{ $vcd->{$code}->{nets} }) { print "V$i ($net->{name}) vsource type=pwl wave=[0p 0]\n"; $i++; } } __END__ V0 (VBGOK_H) vsource type=pwl wave=[0p 0] V1 (YOUT_RC_CAL) vsource type=pwl wave=[0p 0] V2 (CLKO_RXADC_96M) vsource type=pwl wave=[0p 0] V3 (AGC_IF_CAP[2:0]) vsource type=pwl wave=[0p 0] V4 (AGC_IF_CAP[2:0]) vsource type=pwl wave=[0p 0] V5 (BBAGC_AVWIN[1:0]) vsource type=pwl wave=[0p 0] V6 (BBAGC_AVWIN[1:0]) vsource type=pwl wave=[0p 0] V7 (CKO_HFOSC_2DIV12) vsource type=pwl wave=[0p 0] V8 (XO32K_VCOUT) vsource type=pwl wave=[0p 0] V9 (YOUT_RC_CAL_PGA) vsource type=pwl wave=[0p 0] V10 (ABB_BIAS_EN) vsource type=pwl wave=[0p 0] V11 (TXMIX_EN) vsource type=pwl wave=[0p 0] V12 (BBPLL_CLKO_DIG_96M) vsource type=pwl wave=[0p 0]

    If you need more help, you have to describe what your desired "wave=..." means. How does this relate to your VCD file data? How does "199p" relate to your VCD data for BBPLL_CLKO_DIG_96M? Show the code you've written and describe in detail how your actual output differs from your desired output.

      1.the original vcd file "$dumpoff $end" "#3537871350",so 't0' is 3537871350 , output is 0p
      2. because the vcd file output will be Cadence spectre analog input ,so for example BBPLL_CLKO_DIG_96M's time squence 't0' value is '0' , and the next time squence 't1' value is '1', I want to insert time sequence t1-1 and value '0', vice versa...
      3. value '0' output is '0', value '1' output is 'VDD/2'

      so the output wave of BBPLL_CLKO_DIG_96M is
      [ 0p 0 (3537876550-3537871350-1)p 0 (3537876550-3537871350)p VDD/2 (3537881760-3537871350-1)p VDD/2 (3537881760-3537871350)p 0 (3537886970-3537871350-1)p 0 (3537886970-3537871350)p VDD/2 ...... ]
      ps. please calculate the result in ()