use 5.010;
use warnings;
use strict;
my $port_name = quotemeta 'sdm_yout_i[1]';
while (<DATA>) {
    if (/\.([0-9a-z_]*?) \(.*?${port_name} .*?,/ ) {
        print '$port_name = ';
        say $port_name;
        print 'cell name = ';
        say $1;
    }
}

__DATA__
 .dout_sar ( dout_sar ) , .dcoc_status ( dcoc_status ) ,     .sdm_yout
+_i ( {sdm_yout_i[1] , n145 } ) , .sdm_yout_q ( sdm_yout_q ) ,
[download]

Outputs:

$port_name = sdm_yout_i\[1\]
cell name = dout_sar
[download]

If you plan on parsing Verilog code, consider Verilog-Perl

Thanks everybody about your kindly reply, following is my code according your replies, and the output which I want :

#!/usr/bin/perl
use 5.010;
use strict;
use warnings;

my $port_name = 'sdm_yout_i[1]';
open my $fh,         "tt.txt"     or die $!;
while (<$fh>)
{
        if  (/\.([0-9a-z_]*?) \( \{.*?\Q$port_name\E .*?,/) {
            print '$port_name = ' ; say $port_name;
            print '$cell name = ' ; say $1;
    }
    
}
[download]

Outputs:

 
$port_name = sdm_yout_i[1]
$cell name = sdm_yout_i
[download]

if  (/\.([0-9a-z_]*?) \(.*?\Q$port_name\E .*?,/) {
[download]

Have a look at quotemeta.

The characters [] are special in regexes, and you need to escape them with \Q...\E aka quotemeta. If I replace ${port_name} with \Q$port_name\E, I get the output "$port_name = sdm_yout_i[1]  cell name = dout_sar". If you want the "cell name" to be "sdm_yout_i", you need to further restrict your regex and replace the .*? just before $port_name with something like \W*.

But this still all feels a bit like a hack. You've been advised to use real Verilog parsers like Verilog::VCD and Verilog-Perl in four separate threads now (out of five total). Perhaps it's about time you looked into getting those installed?

You need to escape the ['s and ]'s.  qr"..." and \Q and \E are useful for that. Consider:

my $haystack = 'lets test[1] this thing $string';
my @tests = ('test[1]', '\Etest[1]\Q', 'test\[1\]');
@tests = map {$_, qr"\Q$_\E"} @tests;

print "Check $_:" . ($haystack =~ /($_)/ ? "got $1\n" : "no match\n") 
+for @tests;
[download]

Check test[1]:no match
Check (?^:test\[1\]):got test[1]
Check \Etest[1]\Q:no match
Check (?^:\\Etest\[1\]\\Q):no match
Check test\[1\]:got test[1]
Check (?^:test\\\[1\\\]):no match
[download]

I modified the regexp a little. You don't need memory braces because variable $& contains the match and '+?' turns the regexp non-greedy.

use strict;
use warnings;
use 5.010;

my $port_name = 'sdm_yout_i[1]';

$port_name =~ s/\[|\]/\\$&/g; # escaping [ and ]

while (<DATA>)
{
    if  ( /\.[0-9a-z_]+ \( {${port_name}.+?\)/ ) {
        print '$port_name = ' ; say $port_name;
        print 'cell name = ' ; say $&;
    }
}

__DATA__
.dout_sar ( dout_sar ) , .dcoc_status ( dcoc_status ) , .sdm_yout_i ( 
+{sdm_yout_i[1] , n145 } ) , .sdm_yout_q ( sdm_yout_q )
[download]

Thanks pme another method to solve , following is my code and what I want :

 
#!/usr/bin/perl
use 5.010;
use strict;
use warnings;

my $port_name = 'sdm_yout_i[1]';
$port_name =~ s/\[|\]/\\$&/g; # escaping [ and ]
open my $fh,         "tt.txt"     or die $!;
while (<$fh>)
{
    if  ( /\.([0-9a-z_]+?) \( \{.*?${port_name} .*?,/ ) {
            print '$port_name = ' ; say $port_name;
            print '$cell name = ' ; say $1;
    }
    
}
[download]

Output :

 
$port_name = sdm_yout_i\[1\]
$cell name = sdm_yout_i
[download]