Re: Regular Expressions with varialbe with "[]" (Verilog)

quotemeta:

use 5.010;
use warnings;
use strict;
my $port_name = quotemeta 'sdm_yout_i[1]';
while (<DATA>) {
    if (/\.([0-9a-z_]*?) \(.*?${port_name} .*?,/ ) {
        print '$port_name = ';
        say $port_name;
        print 'cell name = ';
        say $1;
    }
}

__DATA__
 .dout_sar ( dout_sar ) , .dcoc_status ( dcoc_status ) ,     .sdm_yout
+_i ( {sdm_yout_i[1] , n145 } ) , .sdm_yout_q ( sdm_yout_q ) ,
[download]

Outputs:

$port_name = sdm_yout_i\[1\]
cell name = dout_sar
[download]

If you plan on parsing Verilog code, consider Verilog-Perl

Comment on Re: Regular Expressions with varialbe with "[]" (Verilog) Select or Download Code

Replies are listed 'Best First'.
Re^2: Regular Expressions with varialbe with "[]" (Verilog) by herman4016 (Acolyte) on Mar 12, 2015 at 02:27 UTC
Thanks everybody about your kindly reply, following is my code according your replies, and the output which I want : `#!/usr/bin/perl use 5.010; use strict; use warnings; my $port_name = 'sdm_yout_i[1]'; open my $fh, "tt.txt" or die $!; while (<$fh>) { if (/\.([0-9a-z_]?) \( \{.?\Q$port_name\E .*?,/) { print '$port_name = ' ; say $port_name; print '$cell name = ' ; say $1; } }` [download] Outputs: `$port_name = sdm_yout_i[1] $cell name = sdm_yout_i` [download]	[reply] [d/l] [select]

Replies are listed 'Best First'.

Re^2: Regular Expressions with varialbe with "[]" (Verilog)
by herman4016 (Acolyte) on Mar 12, 2015 at 02:27 UTC

Thanks everybody about your kindly reply, following is my code according your replies, and the output which I want :

#!/usr/bin/perl
use 5.010;
use strict;
use warnings;

my $port_name = 'sdm_yout_i[1]';
open my $fh,         "tt.txt"     or die $!;
while (<$fh>)
{
        if  (/\.([0-9a-z_]*?) \( \{.*?\Q$port_name\E .*?,/) {
            print '$port_name = ' ; say $port_name;
            print '$cell name = ' ; say $1;
    }
    
}
[download]

Outputs:

 
$port_name = sdm_yout_i[1]
$cell name = sdm_yout_i
[download]

[reply]
[d/l]
[select]