jag194u has asked for the wisdom of the Perl Monks concerning the following question:

HI monks,

i have several lines of code as below 

write_x("top.inst1.inst2.reg",32'h30,status,"string");
write_x("mod.ins5.ins7.val",{24'h0,4'h2,variable1,variable2},status,"s
+tring");

[download]

i am trying to change the above 2 lines to the format 

writing.reg("top.inst1.inst2.reg").write(status,32'h30);
writing.reg("mod.ins5.ins7.val").write(status,{24'h0,4'h2,variable1,va
+riable2});

[download]
i have written a script 
open (input_file,"input.txt") || die"cannot open file"; 
open (output_file,"output.txt") || die"cannot open file";

$line = input_file;
while ($line ne "") {
@words = split(/[(,"]/,$line);
if($word[0]=~/write_x/)
        {
      foreach(@word)
  {
    print $index;
          if( $_=~/write_x/) {
          
          print output_file_ex ("writing.reg(\"$word2\").write($word[5
+,]$word[4]);\n");}
          
}
        else { 
 print output_file_ex ($line); }
    $line = <input_file>;
}

[download]
the problem is for the second line...{24'h0,4'h2,variable1,variable2} i need to find a way to say the split command to exclude , in this {} ..Thanks in advance

Replies are listed 'Best First'.
Re: want to ignore pattern under{} in split command
by toolic (Bishop) on May 27, 2015 at 17:19 UTC
    If your input will have at most 1 set of curlies per line, this works: 
    use warnings;
use strict;

while (<DATA>) {
    chomp;
    my $concat;
    if (s/({.+})/{}/) { # replace curlies' contents with just curlies 
+for now
        $concat = $1;
    }
    my @words = split /[(,]/;
    $words[2] = $concat if $concat;
    print "writing.reg($words[1]).write($words[3],$words[2]);\n";
}

__DATA__
write_x("top.inst1.inst2.reg",32'h30,status,"string");
write_x("mod.ins5.ins7.val",{24'h0,4'h2,variable1,variable2},status,"s
+tring");

    [download]

    It looks like you are parsing Verilog. If so, take a look at Verilog-Perl because (you are about to find out that) parsing Verilog is not trivial.

[reply]
[d/l]
Re: want to ignore pattern under{} in split command
by AnomalousMonk (Archbishop) on May 27, 2015 at 23:12 UTC

    As toolic has remarked, it looks like you want to write a Verilog parser for yourself rather than use an established module (employment insurance?). If so, the recent saga of herman4016 may be helpful. Also, typing 'Verilog' into Super Search may help.

    Give a man a fish:  <%-(-(-(-<

[reply]
[d/l]
      Thanks toolic ...it worked for me.
[reply]

        You're very welcome — it was good for me, too. But I am not toolic.

        Give a man a fish:  <%-(-(-(-<

[reply]
[d/l]

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