Re^4: want to ignore pattern under{} in split command

HI Toolic,

similar to {*} can be treated as {} in the earlier solution by you

if i have

write_x($psprintf("mod.ins[%d].ins[%d].val",1,2),{24'h0,4'h2,variable1
+,variable2},status,"s
+tring");
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any inputs how to make the split command to read the below into single word..i have tried few ways but in vain.

$psprintf("mod.ins[%d].ins[%d].val",1,2)
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Re^5: want to ignore pattern under{} in split command by AnomalousMonk (Archbishop) on May 28, 2015 at 19:50 UTC
Hi jag194u. I'm still not toolic, but here's an answer to your specific question along with a different general approach to your problem. (Of course, you don't give full input and output strings for your new `$psprintf(...)` variation and I've had to guess, but maybe I'm close.) However, I'm afraid I'm just leading you further down a dead-end street: what you really need is a real Verilog (it looks like) parser rather than a jury-rigged regex approach, but anyway... Give this a try, see what you think. You also don't say what Perl version you have available, and this needs version 5.10+. File `ToyVerilog.pm`: Read more... (3 kB) File `ToyVerilog.t`: Read more... (3 kB) Output: c:\@Work\Perl\monks\jag194u>perl ToyVerilog.t ok 1 - use ToyVerilog; ok 2 - writing.reg("top.inst1.inst2.reg").write(status,32'h30); ok 3 - writing.reg("mod.ins5.ins7.val").write(status,{24'h0,4'h2,varia +ble1,variable2}); ok 4 - writing.reg($psprintf("mod.ins[%d].ins[%d].val",1,2)).write(sta +tus,{24'h0,4'h2,variable1,variable2}); ok 5 - writing.reg("top.inst1.inst2.reg").write(status,32'h30); foo # other stuff # bar writing.reg("mod.ins5.ins7.val").write(status,{24'h0,4'h2,variab +le1,variable2}); # some more things # baz writing.reg($psprintf("mod.ins[%d].ins[%d].val",1,2)).write(stat +us,{24'h0,4'h2,variable1,variable2}); boff # whatever else # ok 6 - no warnings 1..6 [download] Give a man a fish: `<%-(-(-(-<`	[reply] [d/l] [select]

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Re^5: want to ignore pattern under{} in split command
by AnomalousMonk (Archbishop) on May 28, 2015 at 19:50 UTC

Hi jag194u. I'm still not toolic, but here's an answer to your specific question along with a different general approach to your problem. (Of course, you don't give full input and output strings for your new $psprintf(...) variation and I've had to guess, but maybe I'm close.) However, I'm afraid I'm just leading you further down a dead-end street: what you really need is a real Verilog (it looks like) parser rather than a jury-rigged regex approach, but anyway... Give this a try, see what you think. You also don't say what Perl version you have available, and this needs version 5.10+.

File ToyVerilog.pm:

Read more... (3 kB)

Output:

c:\@Work\Perl\monks\jag194u>perl ToyVerilog.t
ok 1 - use ToyVerilog;
ok 2 - writing.reg("top.inst1.inst2.reg").write(status,32'h30);
ok 3 - writing.reg("mod.ins5.ins7.val").write(status,{24'h0,4'h2,varia
+ble1,variable2});
ok 4 - writing.reg($psprintf("mod.ins[%d].ins[%d].val",1,2)).write(sta
+tus,{24'h0,4'h2,variable1,variable2});
ok 5 - writing.reg("top.inst1.inst2.reg").write(status,32'h30); foo
# other stuff
# bar writing.reg("mod.ins5.ins7.val").write(status,{24'h0,4'h2,variab
+le1,variable2});
# some more things
# baz writing.reg($psprintf("mod.ins[%d].ins[%d].val",1,2)).write(stat
+us,{24'h0,4'h2,variable1,variable2}); boff
# whatever else
#
ok 6 - no warnings
1..6
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