Verilog Preproc callbacks

richmaes has asked for the wisdom of the Perl Monks concerning the following question:

I'm trying to get familiar with verilog::preproc and so I took the example code and it worked just great. Then I decided that I wanted to try out a callback because the example doesn't do what I need, but then I realized, I don't know how callback work in perl. I kind of expected that relative to a class, that I was basically just making an override, or something that called the original plus something additional. Having said, that....I still don't know what I am doing... so I ask you. Below is the example plus two what I believe are callback functions supported by verilog::preproc. I kind of expected I would see these prints going off as read through some verilog lines. My guess is that the callbacks need to be reference to $vp somehow, but I am sure how to do appropriately. Any pointers to relevant tutorials or assistance is appreciated.

#!/usr/bin/perl
# This is a complete verilog pre-parser!
# For a command line version, see vppreproc
use Verilog::Getopt;
use Verilog::Preproc;
 
my $opt = new Verilog::Getopt;
@ARGV = $opt->parameter(@ARGV);
 
my $vp = Verilog::Preproc->new(options=>$opt,);
$vp->open(filename=>"../common/tiri_defines.vh");
while (defined (my $line = $vp->getline())) {
   print $line;
}

sub define {
   my $self = shift;
   my $defname = shift;
   my $value = shift;
   my $params = shift;

   print "defname = $defname\n";
   print "  value = $value\n";
   print " params = $params\n";
}

sub def_exists  {
   my $self = shift;
   my $defname = shift;
   print "DEF_EXISTS\n";
}
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Re: Verilog Preproc callbacks by tangent (Parson) on Aug 19, 2015 at 01:28 UTC
I am not familiar with the module but from a quick look at the docs it seems that, in order to implement callbacks, you need to create your own class which inherits from Verilog::Preproc. To experiment, you could add a couple of lines to your script like this (untested): #!/usr/bin/perl use Verilog::Getopt; use Verilog::Preproc; my $opt = new Verilog::Getopt; @ARGV = $opt->parameter(@ARGV); # call new on derived class my $vp = My::Verilog::Preproc->new(options=>$opt); $vp->open(filename=>"../common/tiri_defines.vh"); while (defined (my $line = $vp->getline())) { print $line; } package My::Verilog::Preproc; # define derived class use parent qw(Verilog::Preproc); # inherit from Verilog::Preproc sub define { my $self = shift; my $defname = shift; my $value = shift; my $params = shift; print "defname = $defname\n"; print " value = $value\n"; print " params = $params\n"; } sub def_exists { my $self = shift; my $defname = shift; print "DEF_EXISTS\n"; } 1; [download]	[reply] [d/l]
Re^2: Verilog Preproc callbacks by richmaes (Initiate) on Aug 20, 2015 at 20:34 UTC
That worked perfectly. Thanks!	[reply]