I am not familiar with the module but from a quick look at the docs it seems that, in order to implement callbacks, you need to create your own class which inherits from Verilog::Preproc. To experiment, you could add a couple of lines to your script like this (untested):

#!/usr/bin/perl
use Verilog::Getopt;
use Verilog::Preproc;
 
my $opt = new Verilog::Getopt;
@ARGV = $opt->parameter(@ARGV);
 
# call new on derived class
my $vp = My::Verilog::Preproc->new(options=>$opt);

$vp->open(filename=>"../common/tiri_defines.vh");
while (defined (my $line = $vp->getline())) {
   print $line;
}


package My::Verilog::Preproc;  # define derived class
use parent qw(Verilog::Preproc); # inherit from Verilog::Preproc

sub define {
   my $self = shift;
   my $defname = shift;
   my $value = shift;
   my $params = shift;

   print "defname = $defname\n";
   print "  value = $value\n";
   print " params = $params\n";
}

sub def_exists  {
   my $self = shift;
   my $defname = shift;
   print "DEF_EXISTS\n";
}
1;
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