Hey Perl monks! I'm trying to parse a verilog file and would like to get all the module names, input/output port names, whether they're inputs/outputs and the input/output sizes for them. For example:

module  mux_test(
  din_0      , 
  din_1      , 
  sel        , 
  mux_out      
 );
 input din_0, din_1, sel ;
 output [7:0] mux_out; //just as an example
//stuff, stuff, and more stuff 
 endmodule
[download]

I'd like to get: inputs = din_0, din_1, sel;
input size = 1 (for each of them);
outputs = mux_out;
output size = [7:0];
module name = mux_test.
I tried using Verilog::Netlist but I could only get module names and input/outputs but not their sizes. I used this code from user "toolic" and examples on cpan:

sub show_hier {
   # Recursively descend through module hierarchy,
   # printing each module name and full hierarchical
   # specifier, all module port names, and all
   # instance port connections.
   my $mod      = shift;
   my $indent   = shift;
   my $hier     = shift;
   my $cellname = shift;
   if ($cellname) {
       $hier .= ".$cellname";
   }
   else {
       $hier = $mod->name();
   }
   print "${indent}ModuleName=", $mod->name(), "  HierInstName=$hier\n
+";
   $indent .= '   ';

   for my $sig ($mod->ports_sorted()) {
       print $indent, 'PortDir=', sigdir($sig->direction()), ' PortNam
+e=', $sig->name(), "\n";
   }

   for my $cell ($mod->cells_sorted()) {
       for my $pin ($cell->pins_sorted()) {
           print $indent, ' PinName=', $pin->name(), ' NetName=', $pin
+->netname(), "\n";
       }

       show_hier($cell->submod(), $indent, $hier, $cell->name()) if $c
+ell->submod();
   }
}
[download]

How can I get the input/output sizes on top of the names?
Thanks for your help!