in reply to Verilog::Netlist parser

To get the size of a port, use data_type: 
$sig->data_type()

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This is documented in Verilog::Netlist::Port.

The other thread in question is Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist)

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Re^2: Verilog::Netlist parser
by perlUser345 (Acolyte) on May 24, 2016 at 17:16 UTC
    Thank you so much! That's what I was looking for! Don't know how I missed Verilog::Netlist::Port.
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