in reply to Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist)
in thread Verilog parse:vhier to get input/output ports

cant we do without using verilog::netlist ? can i get a glimse of how we can do without using any packages
  • Comment on Re^2: Verilog parse:vhier to get input/output ports (Verilog::Netlist)

In Section Seekers of Perl Wisdom