Verilog parse:vhier to get input/output ports

perlUser345 has asked for the wisdom of the Perl Monks concerning the following question:

Hey perl monks! I'm trying to parse a verilog file and would like to get all the module names, input/output port names, whether they're inputs/outputs and the input/output sizes for them. For example:

module  mux_test(
  din_0      , 
  din_1      , 
  sel        , 
  mux_out      
 );
 input din_0, din_1, sel ;
 output [7:0] mux_out; //just as an example
//stuff, stuff, and more stuff 
 endmodule
[download]

I'd like to get: inputs = din_0, din_1, sel;
input size = 1 (for each of them);
outputs = mux_out;
output size = 8;
module name = mux_test.
I tried using vhier but I could only get module names with: vhier <name> --modules
Is there any other tool I can use to do this and an example related to mine above would be appreciated.
Thanks for your help!

--Update!
Solved the problem! Used Verilog::Netlist and data_type() for the size of inputs/outputs. Thanks toolic!

Comment on Verilog parse:vhier to get input/output ports Download Code

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Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist) by toolic (Bishop) on May 23, 2016 at 17:38 UTC
vhier does not print out ports, but Verilog::Netlist does. Here is an example: Re^3: verilog perl usage (Verilog::Netlist)	[reply]
Re^2: Verilog parse:vhier to get input/output ports (Verilog::Netlist) by perlUser345 (Acolyte) on May 24, 2016 at 16:50 UTC
I did. The problem is I can't get the port sizes for inputs/outputs. Like if it's `input [7:0] test`, how do I get the `[7:0]`?	[reply] [d/l] [select]
Re^2: Verilog parse:vhier to get input/output ports (Verilog::Netlist) by Anonymous Monk on Jun 10, 2016 at 07:51 UTC
cant we do without using verilog::netlist ? can i get a glimse of how we can do without using any packages	[reply]