As toolic has remarked, it looks like you want to write a Verilog parser for yourself rather than use an established module (employment insurance?). If so, the recent saga of herman4016 may be helpful. Also, typing 'Verilog' into Super Search may help.

Give a man a fish:  <%-(-(-(-<

In reply to Re: want to ignore pattern under{} in split command by AnomalousMonk
in thread want to ignore pattern under{} in split command by jag194u

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