Hey perl monks! I'm trying to parse a verilog file and would like to get all the module names, input/output port names, whether they're inputs/outputs and the input/output sizes for them. For example:
module  mux_test(
  din_0      , 
  din_1      , 
  sel        , 
  mux_out      
 );
 input din_0, din_1, sel ;
 output [7:0] mux_out; //just as an example
//stuff, stuff, and more stuff 
 endmodule

[download]
I'd like to get: inputs = din_0, din_1, sel;
input size = 1 (for each of them);
outputs = mux_out;
output size = 8;
module name = mux_test.
I tried using vhier but I could only get module names with: vhier <name> --modules
Is there any other tool I can use to do this and an example related to mine above would be appreciated.
Thanks for your help!

--Update!
Solved the problem! Used Verilog::Netlist and data_type() for the size of inputs/outputs. Thanks toolic!

In reply to Verilog parse:vhier to get input/output ports by perlUser345

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