vhier does not print out ports, but Verilog::Netlist does. Here is an example: Re^3: verilog perl usage (Verilog::Netlist)

In reply to Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist) by toolic
in thread Verilog parse:vhier to get input/output ports by perlUser345

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