If I am not mistaken, it looks like you are parsing a Verilog Value Change Dump (VCD) file. If you have access to Synopsys' VCS simulator -- and that is a big if -- then you should also have acces to the vcat utility.

vcat is very handy in converting a VCD file into a much simpler format for further parsing.

The other simulator vendors may have similar capabilities. It might be worth a look if you have some heavy-duty parsing, just so you avoid re-inventing the wheel, as I have done far too often with VCD:)

Update (12 jan 2012): Verilog::VCD

In reply to Re: Someone please verify this. (Verilog::VCD) by toolic
in thread Someone please verify this. by ksangam

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