in reply to Someone please verify this.

If I am not mistaken, it looks like you are parsing a Verilog Value Change Dump (VCD) file. If you have access to Synopsys' VCS simulator -- and that is a big if -- then you should also have acces to the vcat utility.

vcat is very handy in converting a VCD file into a much simpler format for further parsing.

The other simulator vendors may have similar capabilities. It might be worth a look if you have some heavy-duty parsing, just so you avoid re-inventing the wheel, as I have done far too often with VCD:)

Update (12 jan 2012): Verilog::VCD

  • Comment on Re: Someone please verify this. (Verilog::VCD)

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Re^2: Someone please verify this. (Verilog::VCD)
by Anonymous Monk on Jan 22, 2012 at 05:21 UTC
    I think the Verilog::VCD module is just a VCD parser. Is there any module out there that can make creating VCDs easier? Thanks.
[reply]
      You are right... Verilog::VCD can only be used to parse VCD files. It can not create a VCD file. I am not aware of any CPAN module which can create a VCD file. This looks like an opportunity for you to contribute.

      Why do you need Perl code to create a VCD file? All Verilog simulators can create VCD files.

[reply]
        Thanks for your reply. I do have a requirement to create a VCD from a dump of values (a set of samples captured from an on chip memory) -- so that it is better from readability/debug point of view. Hopefully, when i am done with my script, i can contribute some CreateVCD module -- lets see :) Thanks.
[reply]

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