Apologize if it is difficult to read becoz of the indentation.copy paste in windows from vi!#!/usr/bin/perl use Verilog::Netlist; # set up options so that files can be found use Verilog::Getopt; #push(@INC,'pwd'); my $opt=new Verilog::Getopt; $opt->parameter("-y","i2c",); # prepare netlist #$file='home/vp/roopa/i2c/i2c_master_byte_ctrl.v'; my $nl=new Verilog::Netlist(options=>$opt); foreach my $file('/home/vp/roopa/i2c/i2c_master_top.v') { $nl->read_file(filename=>$file); } #read in any sub modules $nl->link(); $nl->lint(); $nl->exit_if_error(); foreach my $mod($nl->top_modules_sorted) { show_hier($mod, " ","",""); } sub show_hier { my $mod=shift; my $indent=shift; my $hier =shift; my $cellname=shift; if(!$cellname) { $hier=$mod->name; #print "\n",$hier; } else { $hier.=".$cellname"; } printf("%45s %s\n",$indent."Module ".$mod->name,$hier); foreach my$cell($mod->cells_sorted) { printf($indent." Cell %s\n", $cell->name); show_hier($cell->submod,$indent." ", hier,$cell->name) if $cell->submo +d; } }
The script identifies all the modules defined and referenced. The O/p is interpreted as folllows i2c_master_top.v has the following referenced modules-(the ones given as cells)hierarchy given by top_module.cellnameOUTPUT Module i2c_master_top i2c_master_top Cell byte_controller Module i2c_master_byte_ctrl i2c_master_top.byte_cont +roller Cell bit_controller Module i2c_master_bit_ctrl i2c_master_top.byte_cont +roller.bit_controller Cell myarbiter Module arbiter i2c_master_top.myarbiter Cell mypli1 Module mypli i2c_master_top.mypli1 Module mymux mymux
The problem lies with the module mymux The module mymux is defined in i2c_master_byte_ctrl.v But it shows up as a module in i2c_master_top whereas it is defined only in the child module Only if I remove the mymux module from i2c_master_byte_ctrl,then it does not show I first thought that just comparing the outputs from each file would give me the modules which have been duplicated. But mymux is not duplicated and still it shows up in the outputs of i2c_master_top and i2c_master_byte_ctrl. Could you please help me with this? Thanks for your timei2c_master_byte_ctrl i2c_master_bit_ctrl myarbiter mypli
In reply to Re^2: verilog-perl vhier usage
by perlvoyager
in thread verilog-perl vhier usage
by Anonymous Monk
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