Create a smaller code sample which any of us can run, give us some small input, and show us what output you expect.
I am making a logic simulator
For fun? Or have you a need for which the mature EDA industry hasn't provided a solution (free or otherwise). Just in case you were unaware, there are free simulators for the Verilog language, as well as the Verilog-Perl CPAN parser.

In reply to Re: I am designing a logic simulator but stuck. by toolic
in thread I am designing a logic simulator but stuck. by Steven_gerrard

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