my ($Rec,$pc_name);

while (<DATA>)
{
  $pc_name = $1, next if (/^(interface .+)$/);
  $Rec->{$pc_name} ||= undef;  ## let it exist
  $Rec->{$pc_name} = $1 if (/^\s+(switchport description .+)$/);
}

for (sort keys %{$Rec}) {
  my $val = $Rec->{$_} ? $Rec->{$_} : "";
  print "$_ = $val\n";
}

__OUTPUT__

interface fc1/1 = switchport description Trunk
interface fc1/10 = 
interface fc1/11 = switchport description DMX02_FA7CA
interface fc1/12 = 
interface fc1/13 = 
interface fc1/14 = 
interface fc1/15 = 
interface fc1/2 = 
interface fc1/3 = 
interface fc1/4 = 
interface fc1/5 = 
interface fc1/6 = 
interface fc1/7 = switchport description DMX02_FA4CA
interface fc1/8 = 
interface fc1/9 = 
interface mgmt0 =
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This is ok if you don't mind the different order of the output lines.