in reply to Re^4: verilog perl usage (Verilog::Netlist)
in thread verilog perl usage

Does it absolutely require module references for that?
I do not know. You now have as much working experience as I do with Verilog-Perl. It seems reasonable that Verilog::Netlist would require you to provide the sub-module definitions (just as all simulators do). OTOH, I can understand why you might want them to be treated like black boxes. All I can offer is this generic advice:
  1. Read (and re-read) the POD.
  2. Try experimenting with more methods and options.
  3. Start studying the Perl source code. Perhaps the functionality you desire is buried in there. If not, maybe it becomes obvious to you how to alter the source code to do what you want.
  4. Try browsing (or asking a question on) the CPAN Verilog Discussion forum: http://www.cpanforum.com/dist/Verilog-Perl.
  5. As a last resort, try contacting the author. There must be some reason CPAN authors provide an email address :)
  • Comment on Re^5: verilog perl usage (Verilog::Netlist)

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Re^6: verilog perl usage (Verilog::Netlist)
by Anonymous Monk on Mar 15, 2009 at 18:53 UTC
    It turns out to be very simple. :-) It looks as though you weren't printing the instance (cell) names. It did what I wanted when i changed the below line 
    print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname()

    [download]
    to 
    print $indent, ' CellName=', $cell->name(), ' PinName=', $pin->name(),
+ ' NetName=', $pin->netname()

    [download]
    Thanks again
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