Re^6: verilog perl usage (Verilog::Netlist)

It turns out to be very simple. :-) It looks as though you weren't printing the instance (cell) names. It did what I wanted when i changed the below line

print $indent, ' PinName=', $pin->name(), ' NetName=', $pin->netname()
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print $indent, ' CellName=', $cell->name(), ' PinName=', $pin->name(),
+ ' NetName=', $pin->netname()
[download]

Thanks again

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