To get the size of a port, use data_type:
$sig->data_type()

This is documented in Verilog::Netlist::Port.

The other thread in question is Re: Verilog parse:vhier to get input/output ports (Verilog::Netlist)


In reply to Re: Verilog::Netlist parser by toolic
in thread Verilog::Netlist parser by perlUser345

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